“Automatic Exploration of RISC-V Compressed Instruction Set Extensions” (TVL E14)

RISC-V is an open instruction set, that has been in the center of innovative computer architecture research. For an upcoming research project I am looking for a highly-motivated postdoctoral researcher (TVL E14) to lead this exciting project, starting January 1st, 2024, or later. The goal of the research is to evaluate the usage of customized compressed instructions for highly-optimized embedded systems. The research will focus on the following aspects:

• Identifying patterns using modern static and dynamic methods
• Automatic generation of instruction set extensions
• Evaluation of auto-generated instructions using an existing tool to estimate hardware impact
• Evaluation and estimation of software performance impact
• Automatic generation of standardized libraries for digital signal processing and neural networks
• Validation of generated instruction set extensions with real world applications

Your profile:

• Excellent understanding of Hardware-/Software-Interfaces
• Fundamental understanding of compilers and tooling
• Not a must: Knowledge of hardware design
• Ability to lead a small, dedicated research team

What you can expect:

• Exciting industry insights and novel research
• Deep interaction with the RISC-V community, led by a RISC-V expert
• Open Source EDA tooling and community interactions
• Possibility for industry placements
• Relatively good salary for an academic position (TVL E14)

Please get in touch with my if you have any questions or want to apply: stefan.wallentowitz@hm.edu. The position will be available January 1st, 2024, but the research grant depends on an excellent candidate.