The best way to browse my list of publications is on my ORCID page.

  1. Wallentowitz, S. (2022). Current Developments in RISC-V. edaForum22.
  2. Wallentowitz, S., Trummer, C., & Gerbert, P. (2022). Building innovation with RISC-V at TUM Venture Labs. 5th Workshop on RISC-V Activities.
  3. Wallentowitz, S. (2022). RISC-V and Open Source Silicon: Opportunities for Academia and Industry.
  4. Wallentowitz, S. (2022). Efficient Processor Verification with cocotb. FPGA Conference Europe.
  5. Wallentowitz, S. (2022). RISC-V and Open Source Silicon - A Perfect Match. Embedded World Conference.
  6. Wallentowitz, S., Kersting, B., & Dumitriu, D. M. (2022, June). Potential of WebAssembly for Embedded Systems. 2022 11th Mediterranean Conference on Embedded Computing (MECO). https://doi.org/10.1109/meco55406.2022.9797106
  7. Wallentowitz, S. (2021). A Framework for Microarchitecture Traces as Abstraction Layer in Computer Architecture Education. Workshop on Computer Architecture Education (WCAE) 2021.
  8. Wallentowitz, S. (2018). Efficient Inter-Task Communication in Tiled Many-Core System-on-Chip Architectures [Dissertation]. Technische Universität München.
  9. Rösch, S., Rauchfuss, H., Wallentowitz, S., Wild, T., & Herkersdorf, A. (2016). MPSoC application resilience by hardware-assisted communication virtualization. Microelectronics Reliability, 61, 11–16. https://doi.org/10.1016/j.microrel.2016.02.009
  10. Vonbun, M., Wallentowitz, S., Oeldemann, A., & Herkersdorf, A. (2015, August). An Analytic Approach on End-to-End Packet Error Rate Estimation for Network-on-Chip. 2015 Euromicro Conference on Digital System Design. https://doi.org/10.1109/dsd.2015.82
  11. Bauer, L., Henkel, J., Herkersdorf, A., Kochte, M. A., Kühn, J. M., Rosenstiel, W., Schweizer, T., Wallentowitz, S., Wenzel, V., Wild, T., Wunderlich, H.-J., & Zhang, H. (2015). Adaptive multi-layer techniques for increased system dependability. It - Information Technology, 57(3), 149–158. https://doi.org/10.1515/itit-2014-1082
  12. Richter, A., Herber, C., Wallentowitz, S., Wild, T., & Herkersdorf, A. (2015, June). A Hardware/Software Approach for Mitigating Performance Interference Effects in Virtualized Environments Using SR-IOV. 2015 IEEE 8th International Conference on Cloud Computing. https://doi.org/10.1109/cloud.2015.129
  13. Wallentowitz, S., Rosch, S., Wild, T., Herkersdorf, A., Wenzel, V., & Henkel, J. (2014, October). Dependable task and communication migration in tiled manycore system-on-chip. Proceedings of the 2014 Forum on Specification and Design Languages (FDL). https://doi.org/10.1109/fdl.2014.7119361
  14. Damodaran, P. P., Wallentowitz, S., & Herkersdorf, A. (2014). Distributed cooperative shared last-level caching in tiled multiprocessor system on chip. Design, Automation &Amp\Mathsemicolon Test in Europe Conference &Amp\Mathsemicolon Exhibition (DATE), 2014. https://doi.org/10.7873/date.2014.096
  15. Network-on-Chip Protection Switching Techniques for Dependable Task Migration on an Open Source MPSoC Platform. (2014, May). EdaWorkshop.
  16. Vonbun, M., Wallentowitz, S., Feilen, M., Stechele, W., & Herkersdorf, A. (2013, September). Evaluation of hop count advantages of network-coded 2D-mesh NoCs. 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). https://doi.org/10.1109/patmos.2013.6662166
  17. Wallentowitz, S., Wild, T., & Herkersdorf, A. (2013). HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation. In Architecture of Computing Systems – ARCS 2013 (pp. 280–291). Springer Berlin Heidelberg. https://doi.org/10.1007/978-3-642-36424-2_24
  18. Open Tiled Manycore System-on-Chip. (2013). Lehrstuhl für Integrierte Systeme.
  19. Herkersdorf, A., Paul, J., Kumar Pujari, R., Stechele, W., Wallentowitz, S., Wild, T., & Zaib, A. (2013). Potentials and challenges for multi-core processors in robotic applications. In M. Horbach (Ed.), INFORMATIK 2013 – Informatik angepasst an Mensch, Organisation und Umwelt (pp. 2749–2764 ). Gesellschaft für Informatik e.V.
  20. Wallentowitz, S., Lankes, A., Zaib, A., Wild, T., & Herkersdorf, A. (2012, August). A framework for Open Tiled Manycore System-On-Chip. 22nd International Conference on Field Programmable Logic and Applications (FPL). https://doi.org/10.1109/fpl.2012.6339273
  21. Lankes, A., Wild, T., Wallentowitz, S., & Herkersdorf, A. (2012). Benefits of selective packet discard in networks-on-chip. ACM Transactions on Architecture and Code Optimization, 9(2), 1–21. https://doi.org/10.1145/2207222.2207228
  22. Wallentowitz, S., Meyer, M., Wild, T., & Herkersdorf, A. (2011, July). Accelerating collective communication in message passing on manycore System-on-Chip. 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. https://doi.org/10.1109/samos.2011.6045439
  23. Kempf, T., Wallentowitz, S., Ascheid, G., Leupers, R., & Meyr, H. (2010). Analytical and Simulation-based Design Space Exploration of Software Defined Radios. International Journal of Parallel Programming, 38(3-4), 303–321. https://doi.org/10.1007/s10766-009-0127-4
  24. Hardware Support to Exploit Parallelism in Homogeneous and Heterogeneous Multi-Core Systems on Chip. (2010). Springer Verlag.
  25. Kempf, T., Wallentowitz, S., Ascheid, G., Leupers, R., & Meyr, H. (2009, January). A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. 2009 22nd International Conference on VLSI Design. https://doi.org/10.1109/vlsi.design.2009.24
  26. Kempf, T., Karuri, K., Wallentowitz, S., Ascheid, G., Leupers, R., & Meyr, H. (2006). A SW performance estimation framework for early system-level-design using fine-grained instrumentation. Proceedings of the Design Automation &Amp\Mathsemicolon Test in Europe Conference. https://doi.org/10.1109/date.2006.243830